Electronic Components High-Performance CPLD ATF2500C-20GM Programmable Logic Device

The ATF2500C is the highest-density PLD available in a 44-pin surface mount pack- age. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electri- cally-erasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically-erasable technology. This PLD is now available in fully Green or LHF (lead and halide-free) packages.

The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out- puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s three sum terms can be combined to provide up to 12 product terms per sum term with no per- formance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combina- torial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automati- cally reset upon power-up.

Features
• High-performance, High-density, Electrically-erasable Programmable Logic Device
• Fully Connected Logic Array with 416 Product Terms
• 15 ns Maximum Pin-to-pin Delay for 5V Operation
• 24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
• D- or T-type Flip-flops
• Product Term or Direct Input Pin Clocking
• Registered or Combinatorial Internal Feedback
• Backward Compatible with ATV2500B/BQ and ATV2500H Software
• Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
• 44-lead Surface Mount Package and 40-pin DIP Package
• Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously
• 8 Synchronous Product Terms
• Individual Asynchronous Reset per Macrocell
• OE Control per Macrocell
• Functionality Equivalent to ATV2500B/BQ and ATV2500H
• 2000V ESD Protection
• Security Fuse Feature to Protect the Code
• Commercial, Industrial, and Military Temperature Range Offered
• 10 Year Data Retention
• Pin Keeper Option
• 200 mA Latch-up Immunity
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available

Using the ATF2500C Family’s Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are:
• Fully Connected Logic Array – Each array input is always available to every product term. This makes logic placement a breeze.
• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage.
• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources.
• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design.
• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48. Each register has its own clock and reset terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O’s output enable, facilitate true bi-directional I/O design.
• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty.
• Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled.
• User Row (64 bits) – Use to store information such as unit history.

4. Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer.
This feature is critical for state as the nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable during tPR.

Shipping Type		Ship Fee	Lead Time	Processing Time
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	EMS	$25.00-$45.00(0.50KG)	4-15 days
	Air, Sea/air and Sea	$2.00-$3.00(0.10KG)	7-30 days
	FedEx	$20.00-$40.00(0.50KG)	3-7 days

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